In order to test that a data communication channel, such as a high-speed serial optical interface or a hard disk device interface, is functioning properly, a known binary data sequence is typically injected or shifted into the input of the data communication channel, and the output of the data communication channel is then compared to an expected output so as to detect errors. The number of bit errors per unit time is referred to as the bit error rate (BER).
Conventional hardware structures known as pseudo-random binary sequence generators are often used to generate testing sequences. The testing sequences generated by pseudo-random binary sequence (PBRS) generators are “pseudo-random” in the sense that the frequency of occurrence of “1” and “0” symbols is close to, but not exactly, 50%. Hence, such testing sequences appear random even though they are, in reality, deterministic. In other words, once a certain number of consecutive symbols in a testing sequence are known, it is possible to calculate subsequent symbols in the testing sequence, given that the algorithm used to generate the testing sequence is also known. This deterministic characteristic allows a pseudo-random binary sequence checker located at the receiving end of a data communications channel to verify the correctness of the transmitted sequence.
One type of checker for performing the above discussed testing is a serial checker. However, serial checkers consume a large amount of power at high data rates, which can be particularly undesirable for use in electronic devices that run on battery power. Therefore, parallel checkers have been developed. Due to the fact that such parallel checkers receive data bits in parallel as words, their power consumption for a given data rate is substantially less than that of a serial checker.
However, parallel checkers are not without their drawbacks. For example, parallel checkers have a fixed data width at their input, and thus operate only for data words of a given size. In addition, such parallel checkers are often limited to a fixed length of PBRS sequence. Furthermore, such parallel checkers require PBRS test sequences to operate, and in some cases, other types of test sequences may be more preferable.
Therefore, further development in the area of parallel data checkers is needed.